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Dual-Phase, Quick-PWM Controller
for IMVP6+ CPU Core Power Supplies
Current Balance
The MAX17410 integrates the difference between the
current-sense voltages and adjusts the on-time of the
secondary phase to maintain current balance. The cur-
rent balance now relies on the accuracy of the current-
sense resistors instead of the inaccurate, thermally
sensitive on-resistance of the low-side MOSFETs. With
active current balancing, the current mismatch is deter-
mined by the current-sense resistor values and the off-
set voltage of the transconductance amplifiers:
The negative current-limit threshold (forced-PWM mode
only) is nominally -125% of the corresponding valley
current-limit threshold. When the inductor current drops
below the negative current limit, the controller immedi-
ately activates an on-time pulse—DL turns off, and DH
turns on—allowing the inductor current to remain above
the negative current threshold.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signals seen by the current-sense inputs (CSP_, CSN_).
I OS ( IBAL ) = I LMAIN - I LSEC =
V OS(IBAL )
R CS
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier (Steady-State Droop)
The MAX17410 include a transconductance amplifier
where R CS is the effective sense resistance and
V OS(IBAL) is the current-balance offset specification in
the Electrical Characteristics table.
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
Current Limit
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses current-sense resistors
between the current-sense inputs (CSP_ to CSN_) as
the current-sensing elements. If the current-sense sig-
nal of the selected phase is above the current-limit
threshold, the PWM controller does not initiate a new
cycle until the inductor current of the selected phase
drops below the valley current-limit threshold. When
either phase trips the current limit, both phases are
effectively current limited since the interleaved con-
troller does not initiate a cycle with either phase.
Since only the valley current is actively limited, the actu-
al peak current is greater than the current-limit thresh-
old by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the current-
sense resistance, inductor value, and battery voltage.
When combined with the undervoltage protection cir-
cuit, this current-limit method is effective in almost
every circumstance.
The positive valley current-limit threshold voltage at
CSP to CSN equals precisely 1/10th the differential
TIME to ILIM voltage over a 0.1V to 0.5V range (10mV
to 50mV current-sense range). Connect ILIM directly to
V CC to set the default current-limit threshold setting of
22.5mV (typ).
for adding gain to the voltage-positioning sense path.
The amplifier’s input is generated by summing the cur-
rent-sense inputs, which differentially sense the voltage
across either current-sense resistors or the inductor’s
DCR. The amplifier’s output connects directly to the
regulator’s voltage-positioned feedback input (FB), so
the resistance between FB and the output-voltage
sense point determines the voltage-positioning gain:
V OUT = V TARGET - R FB I FB
where the target voltage (V TARGET ) is defined in the
Nominal Output Voltage Selection section, and the FB
amplifier’s output current (I FB ) is determined by the
average value of the current-sense voltages:
I FB = G m ( FB ) × V CSPAVG - CSN
where V CS = V CSPAVG-CSN is the average current-
sense voltage between the CSPAVG and the CSN_
pins, and G m(FB) is typically 1.2mS as defined in the
Electrical Characteristics table.
Differential Remote Sense
The MAX17410 includes differential, remote-sense
inputs to eliminate the effects of voltage drops along the
PCB traces and through the processor’s power pins.
The feedback-sense node connects to the voltage-posi-
tioning resistor (R FB ). The ground-sense (GNDS) input
connects to an amplifier that adds an offset directly to
the target voltage, effectively adjusting the output volt-
age to counteract the voltage drop in the ground path.
Connect the voltage-positioning resistor (R FB ), and
ground-sense (GNDS) input directly to the processor’s
remote-sense outputs as shown in Figure 1.
26
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